1. Field of the Invention
The present invention relates to a high density nonvolatile memory high-density, a fabrication method thereof, and a method of reading data therefrom. More particularly, it relates tea self,alignment-type nonvolatile memory of split structure which is provided with a memory cell array wherein a plurality of memory cells, each having a auxiliary gate, a control gate and a floating gate, are arranged in a matrix and which suitably permits an increase of its capacity.
2. Description of the Prior Art
The unit cell of a nonvolatile memory of split structure is composed of a silicon substrate provided with a source and a drain, a first electrode (AG) formed on the silicon substrate, a floating gate (FG) formed on the side wall of the first electrode, and a second electrode (CG) provided on the floating gate so as to control the potential of the floating gate. These unit cells are arranged in X and Y directions to form a matrix.
FIG. 9 shows two memory cells C11 and C12 arranged in the X direction wherein the source of the memory cell C11 and the drain of the memory cell C12 are continuously formed. Memory cells C21 and C22 are arranged respectively in the Y direction with respect to the memory cells C11 and C12. Memory cells C11 and C21 (C12 and C22) are connected by an impurity diffused layer which functions as a source or a drain without necessitating a contact region for connecting the impurity diffused layer to a metal wiring layer, so that the size of the cell array can be reduced and hence the high-density of the memory device can be realized.
Reading data from a nonvolatile memory of this type has been performed, by, applying predetermined voltages V.sub.CG.READ, V.sub.AG.READ, and V.sub.D.READ to CG1, AG1, and BL1, respectively, when C11 is a selected cell in FIG. 9. In other words, as shown in FIG. 10, the selected cell, the predetermined voltages V.sub.CG.READ, V.sub.AG.READ, and V.sub.D.READ are applied to the second electrode (CG) 81, first electrode (AG) 82 and the drain 83, respectively in the selected cell.
However, nonvolatile memories of this arrangement have following disadvantages in reading data therefrom.
When the memory cell C11 is the selected cell in FIG. 9, the second electrode (CG1) is supplied with voltage to be put in the high state as well as the first electrode (AG1) and a bit line BL1 are supplied with voltage to be put in the high state. Then, the first electrode (AG1) and drain of a memory cell C21 which is adjacent in the Y direction are also supplied with voltage to be put in the high state, thereby turning on the AG1 and transistor T21 for the memory cell C21. In this case, if the memory cell C21 is in the state of over erase as shown in FIG. 11, there is a possibility that a leak current, designated by an arrow 91, will flow through the memory cell C21. The second electrode (CG2), the first electrode (AG2), and bit lines BL0 and BL1 in FIG. 9 are in the low state.
When a memory cell C12 (instead of the memory cell C11) is the selected cell, there is also a possibility as mentioned above that a leakage current will flow through the memory cell C22 if the memory cell C22 is in the over-erase state.
Consequently, lacking in the prior art is a memory cell of novel structure for preventing a leakage current from flowing in an unselected cell which is in the same word line as the selected cell and which is in the over-erase state.